Dwarkesh Patel interviews Intel specialists about process development, yield improvement and the move from FinFETs to gate-all-around transistors. They explain tradeoffs involving high numerical aperture lithography and backside power.
The discussion explores experimental materials, transistor stacking and hybrid bondingHybrid bonding joins chips or wafers by bonding both their insulating surfaces and aligned metal contacts, creating dense electrical connections. to improve chip connectionsAI compute infrastructure is the hardware, facilities, networks, power, cooling, storage, and software used to train and run AI models.. Intel leaders also describe equipment supply constraints and the economics of expanding foundry capacityAI compute capacity is the available ability of hardware and supporting systems to perform AI training or inference work over time.. Forward-looking statements are the speakers’ assessments.
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